1. Field of the Invention
This invention relates to a clock synchronizing circuit, and more particularly to a clock synchronizing circuit suited to use in a usual digital system.
2. Description of the Related Art
An example of a synchronizing circuit for the related art is shown in FIG. 1. In this specification, clock synchronizing circuits and synchronizing circuit elements carry out signal processing and logic operations while connected with each other via clock signals taken from a common clock line.
The synchronizing circuit in FIG. 1 actually consists of a number of flip-flops and gates connected together in cascade but in this diagram just the combination of the three flip-flops FF1 to FF3 and the two gates G1 and G2 is shown.
In this diagram, data DT is sent to the input of the D-type flip-flop FF1 via the terminal 101. The data DTa outputted from the D-type flip-flop FF1 is sent to the gate G1, and the data DTb outputted from this gate G1 is then sent to the input terminal D of the D-type flip-flop FF2. The data DTc outputted from the D-type flip-flop FF2 is sent to the gate G2 and the data DTd outputted from this gate G2 is then sent to the input terminal D of the D-type flip-flop FF3.
The character L indicates the line that provides the clock signal (clock line), with the clock signal CLK being provided via input terminal 102. Clock signals CLK 1, CLK 2 and CLK 3 are then provided via the clock line L, which is the nearest, to each of the flip-flops FF1, FF2 and FF3. As a signal delay occurs depending on the length of the clock line L, the clock signals CLK 1 to CLK 3 are not of equal phase.
FIG. 2 is a timing diagram for describing this relationship.
The data DT1 (=DT) provided to the input terminal D of the D-type flip-flop at the time t0 shown in FIG. 2B is taken into the D-type flip-flop FF1 on the rising edge of the clock signal CLK 1 at the time t1 shown in FIG. 2A. The period of time until the time t2 when the data DT1 which was taken in is outputted from the output terminal Q as the data DTal is the period of time for processing within the D-type flip-flop tFF, which is the internal delay time within the D-type flip-flop FF1.
The period of time between the time t2 and the data DTa1 undergoing prescribed signal processing before being outputted from the output terminal as the data DTb1 at the time t4 is tG. There is also the time known as the wiring delay time tSK (skew) between the time t1 at which the clock signal CLK 1 rises and the time t3 at which the clock signal CLK 2 rises and the time period known as the "hold time" tHOLD between the times t3 and t4.
A specific example of other parts of the circuit shown in FIG. 1 is shown in FIG. 3.
In the example in FIG. 3, registers R11 to R13 made up of D-type flip-flops are arranged in front of and behind an arithmetic logic unit (ALU). The clock signal CLK is provided to the circuit from the terminal 106 so as to provide synchronized operation. Numerals 103 and 104 indicate terminals for inputting data. Signal delays also occur between the clock signals provided to each of the registers R11 to R13 in this kind of circuit construction the signals going around the clock line L.
Skew which accompanies the formation of the line L (the clock line) for providing the clock signal CLK also occurs. The skew depends on the place from which these signals are taken and if these positions are different the skew becomes large. This means that the hold time tHOLD for the D-type flip-flop FF in the next stage becomes short, so that in the worst case the correct data is not latched and errors occur.